WRS-LJ supports optional oscillator replacement with alternative VCTCXO or OCXO models, such as Abracom ABLNO, Crystek CCHD-950, or IQOV-162-3. This allows precise tuning of jitter performance and phase stability to meet specific network requirements.
White Rabbit Switch with Low Jitter Daughterboard (WRS-LJ)
AvailableAsk
The legendary White Rabbit Switch (WRS) now features a new Low Jitter (WRS-LJ) module, which significantly reduces phase noise on the 10 MHz and PPS signals. This improvement is achieved through an external phase-locked loop (PLL) and a VCTCXO oscillator. The module also enables these enhancements in Boundary Switch mode. Installed inside the existing WR-S3/18 switch on the Switch Control Board (SCB), WRS-LJ requires only a new external 10 MHz input, replacing the standard input when the device operates as a Grand Master.
Technical Specifications
Specification
• Modified ADEV at 1 s: < 5×10⁻¹³ (typ. 4×10⁻¹³)
• Modified ADEV at 10 s: < 5×10⁻¹⁴
• Jitter (10 Hz–100 kHz): < 2 ps RMS (typ. 1.5 ps RMS)
Hardware
• 10 MHz clock input for Grand Master operation with extended input power range
• Low phase-noise PLL AD9516-4 for clock synthesis
• Low-jitter 20 MHz VCTCXO
- Connor-Winfield DOT050 VCTCXO (DOT050V-020.0M)
• Optional oscillator installation (14×9 mm package):
- Abracom ABLNO VCTCXO
- Crystek CCHD-950 VCTCXO
- IQOV-162-3 OCXO (CMOS output)
• 16-bit DAC AD5662 for oscillator control (used by White Rabbit PTP core)
Applications
• 5G and next-generation telecommunications
• Financial transaction systems
• Power grid synchronization
• Geolocation and positioning
• Scientific infrastructure, including particle accelerators and astronomical observatory networks
Compare
Parameter
WRS with Low Jitter
WRS
Main Function
Improved WRS clock signal stability and precision
Time distribution and synchronization in WR networks
Clock System
External PLL AD9516-4 + 20 MHz VCTCXO
Built-in generators and PLL (CDCM61002, AD9516)
Optional Oscillators
Abracom ABLNO, Crystek CCHD-950, IQOV-162-3 OCXO
None
Jitter
Jitter < 2 ps RMS (typ. 1.5 ps RMS)
Standard WRS level
Frequency Stability (ADEV)
<5×10⁻¹³ at 1 s (typ. 4×10⁻¹³), <5×10⁻¹⁴ at 10 s
Not specified
And There’s More
We offer custom modifications of our hardware, firmware, and gateware, along with technical consulting services in electronic engineering, system design, integration, and testing. For more information, please contact our team.
Useful Links / Downloadable Resources
FAQ
WRS-LJ achieves a modified ADEV of < 5×10⁻¹³ at 1 s (typ. 4×10⁻¹³) and < 5×10⁻¹⁴ at 10 s. Jitter in the 10 Hz–100 kHz range remains below 2 ps RMS (typ. 1.5 ps RMS), ensuring ultra-precise network synchronization for demanding scientific and industrial applications requiring highly stable clocks.